Many integrated circuits today are manufactured using metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) transistor technology. CMOS circuits allow the integration of many transistors into a small area, and offer relatively low power consumption. These features make CMOS technology the technology of choice for such products as microprocessors, microcontrollers, memories, telecommunication circuits, and analog and digital audio circuits.
For quite some time, CMOS circuits have operated using a single five-volt power supply. The five-volt supply has been more than adequate to ensure enough headroom for signal amplifiers, sense amplifiers, and digital logic. Due to the trend toward higher-density logic circuits which are subject to voltage scaling because of transistor geometry changes, such as reduced gate oxide thickness, there is a trend toward lower supply voltages. For CMOS circuits, the lower power supply voltage may be only, for example, 3.3 volts. While some integrated circuits have been designed to operate with this reduced power supply voltage, other circuits continue to require the conventional 5-volt supply. This creates compatibility problems. For example, a microcontroller designed to operate with a 3.3-volt supply may be connected to a bus which also is capable of conducting signals from 5-volt devices. Thus, output buffer circuits designed for operation at a reduced power supply voltage need to be able to interface with devices at the higher power supply voltage.
Exposure to these higher power supply voltages can cause several compatibility problems for the reduced voltage output buffer. FIG. 1 illustrates in partial block diagram and partial schematic form an output buffer circuit 20 according to the prior art, which attempts to solve these problems. Output buffer circuit 20 includes a P-channel MOS transistor 21, N-channel MOS transistors 22-24, P-channel transistors 25-27, and a bonding pad 28. Transistor 21 has a source connected to a power supply voltage terminal labelled "V.sub.DD ", a gate, a drain connected to bonding pad 28, and a bulk electrode. V.sub.DD is a more-positive power supply voltage terminal which has a nominal value of approximately 3.3 volts. Transistor 22 has a drain connected to the drain of transistor 21, a gate connected to V.sub.DD, and a source. Transistor 23 has a drain connected to the source of transistor 22, a gate for receiving a signal labelled "NGATE", and a source connected to a power supply voltage terminal labelled "VSS". V.sub.SS is a more-negative power supply voltage terminal which functions as the common or ground power supply voltage terminal and has a nominal value of 0 volts. Transistor 24 has a first current electrode for receiving a signal labelled "PGATE", a gate connected to V.sub.DD, and a second current electrode connected to the gate of transistor 21. Transistor 25 has a first current electrode connected to the drain of transistor 21, a gate connected to V.sub.DD, and a second current electrode connected to the gate of transistor 21. Transistor 26 has a source connected to the drain of transistor 21, a gate connected to V.sub.DD, and a drain connected to the bulk electrode of transistor 21. Transistor 27 has a source connected to V.sub.DD, a gate connected to bonding pad 28, and a drain connected to the bulk electrode of transistor 21.
Transistor 21 forms the pullup side and transistor 23 forms the pulldown side of output buffer 20. Output buffer 20 includes several features which allow it to operate reliably in systems in which another device is capable of driving the signal on bonding pad 28 to a voltage higher than V.sub.DD, such as 5 volts when V.sub.DD is 3.3 volts. First cascode transistor 22 protects transistor 23 from the high voltages on bonding pad 28, which prevents a full 5 volts from appearing between the drain and gate. Second, transistor 25 prevents a high voltage on bonding pad 28 from causing transistor 21 to conduct to discharge the voltage on bonding pad 28 into V.sub.DD. Transistor 25 becomes conductive when the voltage on bonding pad 28 exceeds V.sub.DD by more than the threshold voltage of transistor 25, designated generally as "V.sub.TP ". Third, since the gate of transistor 21 may become biased above V.sub.DD, transistor 24 serves as a pass transistor to isolate the internal circuitry driving signal PGATE from the excessive voltage. Fourth, the bulk of transistor 21 is biased using a "switched well" technique. When the voltage on bonding pad 28 is at 5 volts, transistor 26 becomes conductive and biases the well to approximately 5 volts. Otherwise when the voltage on bonding pad 28 is a logic low, transistor 27 becomes conductive to bias the bulk of transistor 21 to V.sub.DD.
Despite these protections, however, output buffer 20 creates two new problems which need to be addressed. First, there is a "deadband" of voltage of bonding pad 28, around which the bulk of transistor 21 becomes "floating" (unbiased). This deadband occurs in the range of V.sub.DD .+-.V.sub.TP, or more precisely, between V.sub.DD -V.sub.TP27 and V.sub.DD +V.sub.TP26, where V.sub.TP27 is the V.sub.TP of transistor 27 and V.sub.TP26 is the V.sub.TP of transistor 26. It is generally desirable to prevent any node from floating, or from having excessive voltage across the gate dielectric. This electrical overstress (EOS) causes Fowler-Nordheim tunneling, which over time reduces the threshold of transistor 21 and eventually results in circuit failure when transistor 21 is no longer capable of being fully conductive.
Second, when output buffer 20 is driving, signal PGATE causes transistor 21 to be conductive or not, depending on the data value to be driven. If signal PGATE is at a logic low, then the voltage on the gate of transistor 21 is at a logic low and is at approximately the same voltage as signal PGATE. However, if signal PGATE is at a logic high, then the voltage on transistor 21 is at V.sub.DD -V.sub.TN, where V.sub.TN represents in general the threshold of an N-channel transistor. If output buffer 20 stops driving when the voltage on the gate of transistor 21 is at V.sub.DD -V.sub.TN and an external device connected to bonding pad 28 drives a logic high of 5 volts, then there is no problem. Transistor 25 becomes conductive and drives 5 volts onto the gate of transistor 21. However, a problem occurs if output buffer 20 stops driving when the voltage on the gate of transistor 21 is at V.sub.DD -V.sub.TN and an external device connected to bonding pad 28 drives a logic low. In this case transistor 25 does not become conductive, and the voltage of V.sub.DD -V.sub.TN remains on the gate of transistor 21. This causes transistor 21 to operate near its threshold, and to be somewhat conductive. Transistor 21 then "leaks" and fights the logic low driven by the external device. This leakage can cause radiated interference, increase power consumption, and affect signal timing by slowing the fall time of the signal on bonding pad 28.
These problems can be better understood with reference to FIG. 7, which illustrates a timing diagram useful in understanding the operation of output buffer 20 of FIG. 1. For all signals, the horizontal axis represents time, and approximate time points of interest are designated along the horizontal axis. For all but one signal, the vertical axis represents voltage. For the one additional signal, the vertical axis represents current. Since output buffer 20 is a CMOS output buffer, a logic high voltage is approximately equal to V.sub.DD and a logic low voltage is approximately V.sub.SS. FIG. 7 labels these voltages where useful in understanding the operation of output buffer 20.
FIG. 7 illustrates two relevant time periods. During a first time period which represents the period on the time axis up to time point t5, signal OUTPUT is driven by output buffer 20 which is in an enabled condition, as indicated by a signal labelled "OE" being active at a logic low. After time point t5, signal OE transitions to a logic high, thereby causing output buffer 20 to enter a three-state condition, whereupon external circuitry may drive signal OUTPUT.
At time point t1, signal DATA transitions from a logic high to a logic low. This transition causes both signals NGATE and PGATE' to transition to a logic high. Note however that the logic high level of signal PGATE' is not a full CMOS logic level, and is at substantially (V.sub.DD -V.sub.TN). Note that signal PBULK was floating prior to time t1, and is driven to substantially V.sub.DD at time t2 by transistor 27. Signal OUTPUT transitions to a logic low by the activation of signal NGATE at time t2. Note the significant V.sub.DD -to-V.sub.SS current pulse which is caused by overlap current in transistors 21 and 23.
At time point t3, signal DATA transitions to a logic high. This transition causes both signals NGATE and PGATE' to transition to a logic low. Signal PGATE' returns to a full CMOS logic low level, and signal PBULK again is floating. Signal OUTPUT transitions to a logic high by the activation of signal PGATE' at time t4. Again there is a significant V.sub.DD -to-V.sub.SS current pulse caused by the overlap current in transistors 21 and 23.
At time point t5, signal OE transitions to a logic high, which causes signal NGATE to be inactive at a logic low and signal PGATE' to be inactive at a logic high regardless of the state of DATA, which causes output buffer 20 to be in a three-state condition. Again signal PGATE' is at substantially (V.sub.DD -V.sub.TN), thereby causing transistor 21 to remain partially conductive. Thus, if an external circuit causes signal OUTPUT to transition to a logic low, there is a further V.sub.DD -to-V.sub.SS current pulse when output buffer 20 enters three-state. Furthermore, there is constant leakage through transistor 21 between the current pulses. Signal PBULK is driven to a voltage of V.sub.DD by transistor 27.
At time point t6, signal OUTPUT transitions to a voltage above V.sub.DD, such as 5 volts in the illustrated example. This high voltage level is coupled to signal PGATE' by transistor 25. Once the gate of transistor 21 reaches this voltage, transistor 21 is no longer conductive, eliminating the V.sub.DD -to-V.sub.SS leakage current. Signal PBULK is likewise coupled to signal OUTPUT by transistor 26.